LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 94
LAN9115_05
Manufacturer Part Number
LAN9115_05
Description
Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN9115_05.pdf
(131 pages)
- Current page: 94 of 131
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Revision 1.1 (05-17-05)
5.3.23
BITS
31
DESCRIPTION
EPC Busy: When a 1 is written into this bit, the operation specified in the
EPC command field is performed at the specified EEPROM address. This
bit will remain set until the operation is complete. In the case of a read this
means that the host can read valid data from the E2P data register. The
E2P_CMD and E2P_DATA registers should not be modified until this bit is
cleared. In the case where a write is attempted and an EEPROM is not
present, the EPC Busy remains busy until the EPC Time-out occurs. At that
time the busy bit is cleared.
Note:
E2P_CMD – EEPROM Command Register
This register is used to control the read and write operations with the Serial EEPROM.
Offset:
EPC busy will be high immediately following power-up or reset.
After the EEPROM controller has finished reading (or attempting to
read) the MAC address from the EEPROM the EPC Busy bit is
cleared.
B0h
DATASHEET
94
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
32 bits
TYPE
SC
SMSC LAN9115
DEFAULT
Datasheet
0
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