LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 118

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
6.3
SYMBOL
nCS, nRD
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
A[7:5]
A[4:1]
Data Bus
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
Note: The “Data Bus” width is 16 bits
PIO Burst Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.2 LAN9115 PIO Burst Read Cycle Timing
Table 6.3 PIO Read Timing
DATASHEET
118
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
165
32
13
0
0
0
0
TYP
MAX
30
7
SMSC LAN9115
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns