LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 120

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
6.5
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
In this mode the upper address inputs are not decoded, and any burst read of the LAN9115 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9115. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or
WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS)
or Read Enable (nRD). When either or both of these control signals go high, they must remain high
for the period specified.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
RX Data FIFO Direct PIO Burst Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
Table 6.5 RX Data FIFO Direct PIO Read Timing
DATASHEET
120
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
MIN
165
32
13
0
0
0
0
TYP
MAX
30
7
SMSC LAN9115
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns