LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 100

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.1 (05-17-05)
5.4.3
31-16
BITS
BITS
15-0
31-0
EEPROM ADDRESS
Reserved
Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of
the LAN9115 device. The content of this field is undefined until loaded from the EEPROM at power-
on. The host can update the contents of this field after the initialization process has completed.
Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the
LAN9115 device. The content of this field is undefined until loaded from the EEPROM at power-on.
The host can update the contents of this field after the initialization process has completed.
is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address
0x06 of the EEPROM. Please refer to
details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the
Ethernet physical address.
ADDRL—MAC Address Low Register
The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The
contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM
Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0])
is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from
address 0x04 of the EEPROM. Please refer to
Table 5.7
reception of the Ethernet physical address. Also shown is the correlation between the EEPROM
addresses and ADDRL and ADDRH registers.
0x01
0x02
0x03
0x04
0x05
0x06
Offset:
Default Value:
below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the
Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering
3
FFFFFFFFh
ADDRL[23:16]
ADDRL[31:24]
ADDRH[15:8]
ADDRL[15:8]
DATASHEET
ADDRH[7:0]
ADDRL[7:0]
ADDRN
Section 4.6
100
DESCRIPTION
DESCRIPTION
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Section 4.6
Attribute:
for more information on the EEPROM. Section
Size:
for more information on the EEPROM.
ORDER OF RECEPTION ON
R/W
32 bits
ETHERNET
2
3
4
5
6
1
nd
rd
th
th
th
st
SMSC LAN9115
Datasheet
5.4.3