LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet
LAN9115_05
Related parts for LAN9115_05
LAN9115_05 Summary of contents
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PRODUCT FEATURES Highlights Member of LAN9118 Family; optimized for medium- ■ performance applications Easily interfaces to most 16-bit embedded CPU’s ■ Efficient architecture with low CPU overhead ■ Integrated PHY; supports external PHY via MII ■ interface Supports audio & ...
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LAN9115-MD FOR 100 PIN, TQFP PACKAGE LAN9115-MT FOR 100 PIN, TQFP PACKAGE (GREEN, LEAD-FREE) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © SMSC 2005. All rights reserved. Circuit diagrams and other information relating to SMSC ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TX Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.6 FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet List of Figures Figure 1.1 System Block Diagram Utilizing the SMSC LAN9115 . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 2.1 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 1 General Description The LAN9115 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9115 has ...
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System Memory Embedded Microprocessor/ System Bus Microcontroller Figure 1.1 System Block Diagram Utilizing the SMSC LAN9115 The SMSC LAN9115 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 1.1 Internal Block Overview This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal Block Diagram". PME - Wakup Indicator Power Management Host Bus Interface ...
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The differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer can control or access the TX ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet The host bus interface is the primary bus for connection to the embedded host system. This interface models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. ...
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Chapter 2 Pin Description and Configuration GND_CORE 1 VREG 2 VDD_CORE 3 VSS_PLL 4 XTAL2 5 XTAL1 6 VDD_PLL 7 VDD_REF 8 ATEST 9 RBIAS 10 VSS_REF ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet PIN NO. NAME 43-46,49- Host Data 53,56-59,62- 64 12-18 Host Address 92 Read Strobe 93 Write Strobe 94 Chip Select 72 Interrupt Request 71,73,84,90, Reserved 91 74 10/100 Selector 76 FIFO Select ...
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PIN NO. NAME 79 TXP 78 TXN 83 RXP 82 RXN 87 PHY External Bias Resistor Table 2.4 Serial EEPROM Interface Signals PIN NO. NAME 67 EEPROM Data, EEDIO/GPO3/ GPO3, TX_EN, TX_EN/TX_CLK TX_CLK 68 EEPROM Chip Select 69 EEPROM Clock, ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet PIN NAME SYMBOL NO. 6 Crystal 1 5 Crystal 2 95 Reset 70 Wakeup Indicator SMSC LAN9115 Table 2.5 System and Power Signals BUFFER NUM TYPE PINS XTAL1 lclk 1 XTAL2 Oclk ...
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Table 2.5 System and Power Signals (continued) PIN NAME SYMBOL NO. 100,99 General Purpose ,98 I/O data, nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), nLED3 (Full- Duplex Indicator ). 10 RBIAS 9 Test Pin 2 Internal Regulator Power 20,28, ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.5 System and Power Signals (continued) PIN NAME SYMBOL NO. 3,65 Core Voltage VDD_CORE Decoupling 1,66 Core Ground GND_CORE 7 PLL Power 4 PLL Ground 8 Reference Power 11 Reference Ground ...
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PIN NO. NAME 40 Transmit Clock: 36, 37, Transmit Data [3:0] 38 Transmit Enable 26 Receive Clock 25 Receive Error 33 Collision Detect: 24, 23, Receive Data[3:0] 22 Carrier Sense 29 Receive Data Valid: 30 Management ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.6 MII Interface Signals (continued) PIN NO. NAME 31 Management Data Clock Note 2.2 The external SMI port is selected when SMI_SEL = 1. When SMI_SEL = 0, MDIO is tri- ...
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Chapter 3 Functional Description 3.1 10/100 Ethernet MAC The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host subsystem and the internal Ethernet PHY. The MAC ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.2 Flow Control The LAN9115 Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. 3.2.1 Full-Duplex Flow Control The ...
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Network efficiency: Allows shielding one system resource from traffic not meant for that resource. A workstation in one VLAN is shielded from traffic on another VLAN, increasing that workstation’s efficiency. Broadcast containment: Leakage of broadcast frames from one VLAN to ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet The MAC Function recognizes transmitted and received frames tagged with either one-level or two- level VLAN IDs. The MAC compares the thirteenth and fourteenth bytes of transmit and receive frames to the ...
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Address Filtering Functional Description The Ethernet address fields of an Ethernet Packet, consists of two 6-byte fields: one for the destination address and one for the source address. The first bit of the destination address signifies whether it is ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.4.2.1 Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9115 Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into ...
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Table 3.2 Wake-Up Frame Filter Register Structure Reserved Filter 3 Reserved Command Filter 3 Offset Filter 1 CRC-16 Filter 3 CRC-16 The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether or not ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 3.5 Filter i Offset Bit Definitions FIELD DESCRIPTION 7:0 Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame recognition. The minimum ...
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Destination Address Source Address …………… ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet MODE OF OPERATION D[15:8] Mode 0 (Big Endian Register equal to 0xFFFFFFFF Byte Byte 1 Mode 1 (Big Endian Register not equal to 0xFFFFFFFF)h A1 ...
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If an 0xA5h is not read from the first address, the EEPROM controller will end initialization then the responsibility of the host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet EEPROM Write Busy Bit = 0 Figure 3.3 EEPROM Access Flow Diagram The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is disabled, the EEDIO and ECLK ...
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EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) EWEN (Erase/Write Enable): Enables the ...
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READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA register. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) WRITE (Write Location): ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit ...
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Power Management LAN9115 supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.10.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power Management ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Note 3.7 The host must do only read accesses prior to the ready bit being set. Once the READY bit is set, the LAN9115 is ready to resume normal operation. At this ...
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Power Managment Event Indicators Figure 3. simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS register, which, ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.10.3.2 Energy Detect Power-Down This power-down mode is activated by setting the Phy register bit 17. Please refer to 5.5.8, "Mode Control/Status," on page 111 no energy is present on ...
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Power-On Reset (POR) A Power-On reset occurs whenever power is initially applied to the LAN9115 power is removed and reapplied to the LAN9115. A timer within the LAN9115 will assert the internal reset for approximately 22ms. The ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12 MII Interface - External MII Switching There are two mechanisms that are used to switch between the internal PHY and the external MII port. A LAN driver or other software controlled ...
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Set EXT_PHY_SEL described in ■ the desired MII port. This step switches the RXD[3:0], RX_DV, RX_ER, TXD[3:0], TX_EN, CRS and COL signals to the desired port. Set PHY_CLK_SEL described in ■ the desired port. This must be the same port ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Using SMI, Set Internal PHY and 1 External PHY to a Stable State 2 Halt Transmitter 3 TX Stopped? YES 4 Halt Receiver 5 RX Stopped? YES Set PHY_CLK_SEL 6 to 10b ...
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TX Data Path Operation Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX command ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Last Buffer in Packet Figure 3.13 Simplified Host TX Flow Diagram SMSC LAN9115 init Idle TX Status Available Read TX Status (optional) Check available FIFO space Write TX Command Write Start Padding ...
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TX Buffer Format TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet There is a 16-bit packet tag in the TX command ‘B’ command word. Packet tags may, if host software desires, be unique for each packet (i.e., an incrementing count). The value of ...
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TX COMMAND ‘B’ BITS 31:16 Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status word and can be used by the host to correlate TX status words ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Additionally, The LAN9115 has specific rules regarding the use of transmit buffers when in Store-and- Forward mode (i.e., HW_CFG[SF] = 1). When this mode is enabled, the total space consumed in the ...
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BITS 7 Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility. 6:3 Collision Count. This counter indicates the number of collisions that occurred before the packet was transmitted not valid when excessive ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Note 3.15 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. atomic 16-bit transactions. SMSC LAN9115 Figure 3.15 and Figure 3.16 describe the host write ...
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Data W ritten to the Ethernet Controller 31 TX Com m and 'A' Buff er End Alignment = 1 Data Start Of fset = 7 First Segment = 1 Last Segment = 0 7-Byte Data Start Offset Buff er Size ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.13.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet single buffer as follows: 2-Byte “Data Start Offset” ■ 183-Bytes of payload ...
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TX Data FIFO Underrun If the MIL is not operating in store and forward mode, and the host is unable supply data at the Ethernet line rate, the TX data FIFO can underrun underrun occurs, any ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet The host must use caution when reading the RX data and status. The host must never read more data than what is available in the FIFOs. If this is attempted an underrun ...
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Last Packet Figure 3.17 Host Receive Routine Using Interrupts Figure 3.18 Host Receive Routine with Polling 3.14.1.1 Receive Data FIFO Fast Forward The RX data path implements an automatic data discard function. Using the RX data FIFO Fast Forward bit ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet When performing a fast-forward, there must be at least 4 DWORDs of data in the RX data FIFO for the packet being discarded. For less than 4 DWORDs do not use RX_FFWD. ...
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Host Read Order Last Note 3.16 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. 3.14.3 RX Status Format BITS 31 Reserved. This bit is reserved. Reads 0. 30 Filtering Fail. When ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 11 Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision window (64 bytes). Runt frames are passed on to the host only if the Pass ...
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Chapter 4 Internal Ethernet PHY 4.1 Top Level Functional Description Functionally, the internal PHY can be divided into the following sections: 100Base-TX transmit and receive ■ 10Base-T transmit and receive ■ Internal MII interface to the Ethernet Media Access Controller ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet CODE GROUP SYM 11110 0 0 01001 1 1 10100 2 2 10101 3 3 01010 4 4 01011 5 5 01110 6 6 01111 7 7 10010 8 8 10011 9 ...
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Table 4.1 4B/5B Code Table (continued) CODE GROUP SYM 01000 V INVALID, RX_ER if during RX_DV 01100 V INVALID, RX_ER if during RX_DV 10000 V INVALID, RX_ER if during RX_DV 4.2.2 Scrambling Repeated data patterns (especially the IDLE code-group) can ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet RX_CLK MAC Internal MII 25MHz by 4 bits MLT-3 NRZI NRZI Converter Converter A/D Magnetics MLT-3 Converter 4.3 100Base-TX Receive The receive data path is shown in 4.3.1 100M Receive Input The ...
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Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet (TX_EN is low), the TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with the remote link partner. 4.4.3 10M Transmit Drivers The Manchester encoded data is sent to the analog ...
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Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the internal Serial Management Interface (SMI). The results of the negotiation process are reflected in the Speed Indication bits in register 31, as ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN9115 does not support “Next Page" capability. 4.7 Parallel Detection If the LAN9115 is ...
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Chapter 5 Register Description The following section describes all LAN9115 registers and data ports. Note 5.1 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits wide. transactions. FCh B4h B0h ACh A8h A4h A0h ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.1 Register Nomenclature and Access Attributes SYMBOL DESCRIPTION RO Read Only register is read only, writes to this register have no effect. WO Write Only register is write ...
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The TX data FIFO is write only aliased in 8 DWORD locations (accessed from the bus interface as 8 pairs of atomic 16-bit accesses). The host write to any of the locations since they all access the same ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.1 LAN9115 Direct Address Register Map (continued) BASE ADDRESS + OFFSET SYMBOL ACh AFC_CFG B0h E2P_CMD B4h E2P_DATA B8h - FCh RESERVED 5.3.1 ID_REV—Chip ID and Revision Offset: This register contains ...
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BITS DESCRIPTION 14 Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one to this register clears the de-assertion counter in the IRQ Controller, thus causing a new de-assertion interval to begin (regardless of whether or not the IRQ Controller is currently ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.3 INT_STS—Interrupt Status Register Offset: This register contains the current status of the generated interrupts. Writing the corresponding bits acknowledges and clears the interrupt. BITS 31 Software Interrupt (SW_INT). ...
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BITS 12 Reserved 11 TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data FIFO underruns Data FIFO Overrun Interrupt (TDFO). Generated when the TX data FIFO is full, and another write is attempted Data ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS DESCRIPTION 18 PHY (PHY_INT_EN) 17 Power Management Event Interrupt Enable (PME_INT_EN Status FIFO Overflow (TXSO_EN) 15 Receive Watchdog Time-out Interrupt (RWT_INT_EN) 14 Receiver Error Interrupt (RXE_INT_EN) 13 Transmitter Error ...
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FIFO_INT—FIFO Level Interrupts Offset: This register configures the limits where the FIFO Controllers will generate system interrupts. BITS DESCRIPTION 31-24 TX Data Available Level. The value in this field sets the level, in number of 64 Byte blocks, at ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 15 Force RX Discard (RX_DUMP). This self-clearing bit clears the RX data and status FIFOs of all pending data. When a ‘1’ is written, the RX data and status pointers are ...
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BITS DESCRIPTION 2 TX Status Allow Overrun (TXSAO). When this bit is cleared, data transmission is suspended if the TX Status FIFO becomes full. Setting this bit high allows the transmitter to continue operation with a full TX Status FIFO. ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS DESCRIPTION 16-19 TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the space ...
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BITS DESCRIPTION 4 Serial Management Interface Select (SMI_SEL). This bit is used to switch the SMI port (MDIO and MDC) between the internal PHY and the external MII port. When this bit is cleared to ‘0’, the internal PHY is ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes – TX FIFO Size). The RX Status FIFO size is always equal to 1/16 of the RX FIFO Size. ...
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RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter (RX_DROP) is incremented. RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register Offset: This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN9115. BITS DESCRIPTION 31-24 ...
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BITS DESCRIPTION 9 Wake-On-Lan Enable (WOL_EN) – When set, the PME signal (if enabled with PME_EN) will be asserted in accordance with the PME_IND bit upon a WOL event. When set, the PME_INT will also be asserted upon a WOL ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.14 GPIO_CFG—General Purpose IO Configuration Register Offset: This register configures the GPIO and LED functions. Bits 31 Reserved 30:28 LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output. ...
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Bits 2:0 GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is reflected on GPIOn. When read, GPIOn reflects the current state of the corresponding GPIO pin. GPIO0 – bit 0 GPIO1 – bit 1 GPIO2 – ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.16 GPT_CNT-General Purpose Timer Current Count Register Offset: This register reflects the current value of the GP Timer. BITS DESCRIPTION 31-16 Reserved 15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field ...
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FREE_RUN—Free-Run 25MHz Counter Offset: This register reflects the value of the free-running 25MHz counter. BITS DESCRIPTION 31:0 Free Running SCLK Counter (FR_CNT): Note: This field reflects the value of a free-running 32-bit counter. At reset the counter starts at ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register Offset: This register is used to control the read and write operations with the MAC CSR’s BITS DESCRIPTION 31 CSR Busy. When a 1 ...
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AFC_CFG – Automatic Flow Control Configuration Register Offset: This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9115 will not transmit pause frames or assert back pressure ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS DESCRIPTION 0 Flow Control on Any Frame (FCANY). When this bit is set, the LAN9115 will assert back pressure, or transmit a pause frame when the AFC level is reached and ...
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E2P_CMD – EEPROM Command Register Offset: This register is used to control the read and write operations with the Serial EEPROM. BITS DESCRIPTION 31 EPC Busy: When written into this bit, the operation specified in the ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS DESCRIPTION 30-28 EPC command. This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. A new command must ...
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BITS DESCRIPTION EPC Time-out EEPROM operation is performed, and there is no response from the EEPROM within 30mS, the EEPROM controller will time- out and return to its idle state. This bit is set when a time-out ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.6 LAN9115 MAC CSR Register Map MAC CONTROL AND STATUS REGISTERS INDEX SYMBOL 1 MAC_CR 2 ADDRH 3 ADDRL 4 HASHH 5 HASHL 6 MII_ACC 7 MII_DATA 8 FLOW 9 VLAN1 ...
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BITS 21 Loopback operation Mode (LOOPBK). Selects the loop back operation modes for the MAC. This is only for full duplex mode 1’b0: Normal: No feedback 1’b1: Internal: Through MII In internal loopback mode, the TX frame is received by ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 7-6 BackOff Limit (BOLMT). The BOLMT bits allow the user to set its back-off limit in a relaxed or aggressive mode. According to IEEE 802.3, the MAC has to wait for ...
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EEPROM. The second byte (bits [15:8]) is loaded from address 0x06 of the EEPROM. Please refer to details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would be programmed as shown in load this configuration from the EEPROM are also shown. 31 ...
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HASHL—Multicast Hash Table Low Register Offset: Default Value: This register defines the lower 32-bits of the Multicast Hash Table. Please refer to "HASHH—Multicast Hash Table High Register" BITS 31-0 Lower 32 bits of the 64-bit Hash Table 5.4.6 MII_ACC—MII ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.7 MII_DATA—MII Data Register Offset: Default Value: This register contains either the data to be written to the PHY register specified in the MII Access Register, or the read data from the ...
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BITS 2 Pass Control Frames (FCPASS). When set, the MAC sets the Packet Filter bit in the Receive packet status to indicate to the Application that a valid Pause frame has been received. The Application must accept or discard a ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.10 VLAN2—VLAN2 Tag Register Offset: Default Value: This register contains the VLAN tag field to identify VLAN2 frames. For VLAN frames the legal frame length is increased from 1518 bytes to 1522 ...
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WUCSR—Wake-up Control and Status Register Offset: Default Value: This register contains data pertaining to the MAC’s remote wake-up status and capabilities. BITS 31-10 Reserved 9 Global Unicast Enable (GUE). When set, the MAC wakes up from power-saving mode on ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.8 LAN9115 PHY Control and Status Register (continued) PHY CONTROL AND STATUS REGISTERS INDEX REGISTER NAME (IN DECIMAL) 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion ...
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BITS DESCRIPTION 6-0 Reserved Note 5.2 This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details 5.5.2 Basic Status Register Index (In Decimal): BITS DESCRIPTION 15 100Base-T4. 1 ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.3 PHY Identifier 1 Index (In Decimal): BITS DESCRIPTION 15-0 PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. 5.5.4 PHY Identifier 2 Index ...
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BITS DESCRIPTION 8 100Base-TX Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex 10Mbps with full duplex ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.7 Auto-negotiation Expansion Index (In Decimal): BITS DESCRIPTION 15:5 Reserved 4 Parallel Detection Fault fault detected by parallel detection logic fault detected by parallel detection logic 3 ...
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Special Modes Index (In Decimal): ADDRESS 15-8 Reserved 7:5 MODE: PHY Mode of operation. Refer to 4:0 PHYAD: PHY Address: The PHY Address is used for the SMI address. MODE MODE DEFINITIONS 000 10Base-T Half Duplex. Auto-negotiation disabled. 001 ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.10 Special Control/Status Indications Index (In Decimal): ADDRESS 15:11 Reserved: Write as 0. Ignore on read. 10 VCOOFF_LP: Forces the Receive PLL 10M to lock on the reference clock at all times: ...
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Interrupt Mask Index (In Decimal): BITS DESCRIPTION 15-8 Reserved. Write as 0; ignore on read. 7-0 Mask Bits interrupt source is enabled 0 = interrupt source is masked 5.5.13 PHY Special Control/Status Index (In Decimal): BITS DESCRIPTION ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 6 Timing Diagrams 6.1 Host Interface Timing The LAN9115 supports the following host cycles: Read Cycles: PIO Reads (nCS or nRD controlled) ■ PIO Burst Reads (nCS or nRD controlled) ■ ...
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Table 6.1 Read After Write Timing Rules REGISTER NAME ID_REV IRQ_CFG INT_STS INT_EN BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT ENDIAN FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA 6.1.2 Special Restrictions on Back-to-Back Read Cycles ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet processor is required to wait the specified period of time between read operations of specific combinations of resources. The wait period is dependant upon the combination of registers being read. Performing "dummy" ...
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SYMBOL DESCRIPTION t Read Cycle Time cycle t nCS, nRD Assertion Time csl t nCS, nRD Deassertion Time csh t nCS, nRD Valid to Data Valid csdv t Address Setup to nCS, nRD Valid asu t Address Hold Time ah ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet SYMBOL DESCRIPTION t nCS, nRD Deassertion Time csh t nCS, nRD Valid to Data Valid csdv t Address Cycle Time acyc t Address Setup to nCS, nRD valid asu t Address Stable ...
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Table 6.5 RX Data FIFO Direct PIO Read Timing SYMBOL DESCRIPTION t Read Cycle Time cycle t nCS, nRD Assertion Time csl t nCS, nRD Deassertion Time csh t nCS, nRD Valid to Data Valid csdv t Address, FIFO_SEL Setup ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet FIFO_SEL A[2:1] nCS, nRD Data Bus Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing Note: The “Data Bus” width is 16 bits Table 6.6 RX Data FIFO Direct PIO ...
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A[7:1] nCS, nRD Data Bus Note: The “Data Bus” width is 16 bits SYMBOL DESCRIPTION t Write Cycle Time cycle t nCS, nWR Assertion Time csl t nCS, nWR Deassertion Time csh t Address Setup to nCS, nWR Assertion asu ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet FIFO_SEL A[2:1] nCS, nRD Data Bus Figure 6.6 TX Data FIFO Direct PIO Write Timing Note: The “Data Bus” width is 16 bits Table 6.8 TX Data FIFO Direct PIO Write Timing ...
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Reset Timing nRST Configuration signals Output drive PARAMETER DESCRIPTION T6.1 Reset Pulse Width T6.2 Configuration input setup to nRST rising T6.3 Configuration input hold after nRST rising T6.4 Output Drive after nRST rising 6.9 EEPROM Timing The following specifies ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet SYMBOL DESCRIPTION t EECLK Cycle time CKCYC t EECLK High time CKH t EECLK Low time CKL t EECS high before rising edge of EECLK CSHCKH t EECLK falling edge to EECS ...
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Chapter 7 Operational Characteristics 7.1 Absolute Maximum Ratings* Supply Voltage ................................................................................................................... +3.3V +/- 10% Operating Temperature ..........................................................................................................0°C to 70°C Storage Temperature.........................................................................................................-65°C to 150°C Positive Voltage on any pin, with respect to Ground ........................................................................ 5.5V Negative Voltage on any pin, with ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 7.1 Power Consumption Device Only (continued) D1, Idle D2, Energy Detect Power Down (Cable disconnected) D2, General Power Down Note 7.1 Each LED indicator in use adds approximately ...
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DC Electrical Specifications PARAMETER SYMBOL I Type Input Buffer Low Input Level V ILI High Input Level V IHI IS Type Input Buffer Negative-Going Threshold V ILT Positive-Going Threshold V IHT Schmitt Trigger Hysteresis V HYS ( ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 7.4 100BASE-TX Tranceiver Characteristics PARAMETER Peak Differential Output Voltage High Peak Differential Output Voltage Low Signal Amplitude Symmetry Signal Rise & Fall Time Rise & Fall Time Symmetry Duty Cycle Distortion ...
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Table 7.6 LAN9115 Crystal Specifications Frequency Tolerance @ 25° C Frequency Stability Over Temp Operating Temp Range Shunt Capacitance Load Capacitance Drive Level Table 7.7 LAN9115 Recommended Crystals Fox Electronics Additionally, SMSC recommends a series resistor for the crystal circuit. ...
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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 8 Package Outline Figure 8.1 100 Pin TQFP Package Definition Table 8.1 100 Pin TQFP Package Parameters MIN NOMINAL 0. 1. 15.80 ~ ...