LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 77

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
5.3.5
BITS
BITS
31:0
2-0
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
DESCRIPTION
Byte Test
DESCRIPTION
PHY (PHY_INT_EN)
Power Management Event Interrupt Enable (PME_INT_EN)
TX Status FIFO Overflow (TXSO_EN)
Receive Watchdog Time-out Interrupt (RWT_INT_EN)
Receiver Error Interrupt (RXE_INT_EN)
Transmitter Error Interrupt (TXE_INT_EN)
Reserved
TX Data FIFO Underrun Interrupt (TDFU_INT_EN)
TX Data FIFO Overrun Interrupt (TDFO_INT_EN)
TX Data FIFO Available Interrupt (TDFA_INT_EN)
TX Status FIFO Full Interrupt (TSFF_INT_EN)
TX Status FIFO Level Interrupt (TSFL_INT_EN)
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
RX Data FIFO Level Interrupt (RDFL_INT_EN)
RX Status FIFO Full Interrupt (RSFF_INT_EN)
RX Status FIFO Level Interrupt (RSFL_INT_EN)
GPIO [2:0] (GPIOx_INT_EN).
BYTE_TEST—Byte Order Test Register
This register can be used to determine the byte ordering of the current configuration
Offset:
64h
DATASHEET
77
Size:
32 bits
TYPE
TYPE
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Revision 1.1 (05-17-05)
87654321h
DEFAULT
DEFAULT
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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