LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 119

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
6.4
SYMBOL
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
FIFO_SEL
nCS, nRD
A[2:1]
Data Bus
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
In this mode the upper address inputs are not decoded, and any read of the LAN9115 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9115. Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits
RX Data FIFO Direct PIO Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Table 6.4 PIO Burst Read Timing
DATASHEET
119
MIN
165
13
0
0
0
0
TYP
Revision 1.1 (05-17-05)
MAX
30
40
7
UNITS
ns
ns
ns
ns
ns
ns
ns