LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 48
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LAN9115_05
Manufacturer Part Number
LAN9115_05
Description
Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN9115_05.pdf
(131 pages)
- Current page: 48 of 131
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Revision 1.1 (05-17-05)
3.13.1
3.13.2
TX Buffer Format
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the
TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32-
bit values that are used by the LAN9115 in the handling and processing of the associated Ethernet
packet data buffer. Buffer alignment, segmentation and other packet processing parameters are
included in the command structure. The following diagram illustrates the buffer format.
Figure 3.14, "TX Buffer Format", shows the TX Buffer as it is written into the LAN9115. It should be
noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must
be taken into account when calculating the actual TX data FIFO usage. Please refer to
"Calculating Actual TX Data FIFO Usage," on page 52
actual TX data FIFO usage.
Note 3.14 The LAN9115 host bus interface supports 16-bit bus transfers; internally, all data paths are
TX Command Format
The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command
precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command
‘A’ and TX command ‘B’.
32-bits wide.
transactions.
Host Write
Order
2nd
3rd
Last
1st
Figure 3.14 TX Buffer Format
Figure 3.14
31
DATASHEET
Offset + Data DWORD0
Optional offset DWORD0
Optional offset DWORDn
Optional Pad DWORDn
Optional Pad DWORD0
TX Command 'B'
describes the host write ordering for pairs of atomic 16-bit
TX Command 'A'
Last Data & PAD
48
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
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for a detailed explanation on calculating the
0
Section 3.13.5,
SMSC LAN9115
Datasheet
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