CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet - Page 9

• Manufacturer Part Number: CY7C1480V33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
The CY7C1480V33/CY7C1482V33/CY7C1486V33 supports
secondary cache in systems using either a linear or interleaved
burst sequence. The interleaved burst order supports Pentium
and i486 processors. The linear burst sequence is suited for
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
HIGH. The address presented to the address inputs (A) is stored
into the address advancement logic and the Address Register
while being presented to the memory array. The corresponding
data is allowed to propagate to the input of the Output Registers.
At the rising edge of the next clock the data is allowed to
propagate through the output register and onto the data bus
Document Number: 38-05283 Rev. *K
MODE
TDO
TDI
TMS
TCK
NC
Pin Name
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(continued)
Synchronous
Synchronous
Synchronous
JTAG Serial
JTAG Serial
JTAG Serial
JTAG Clock
Input Static
Output
Input
Input
I/O
–
CO
) is 3.0 ns (250 MHz device).
X
) inputs. A Global Write
1
, CE
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and must remain
static during device operation. Mode Pin has an internal pull up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to V
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
2
, CE
1
is HIGH.
3
) and an
SS
. This pin is not available on TQFP packages.
1
is
within 3.0 ns (250-MHz device) if OE is active LOW. The only
exception occurs when the SRAM is emerging from a deselected
state to a selected state, its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
read cycles are supported. After the SRAM is deselected at clock
rise by the chip select and either ADSP or ADSC signals, its
output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE
CE
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BW
first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BW
signals.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides
byte write capability that is described in the
Read/Write on page
(BWE) with the selected Byte Write (BW
write to only the desired bytes. Bytes not selected during a Byte
Write operation will remain unaltered. A synchronous self-timed
Write mechanism has been provided to simplify the Write
operations.
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be deasserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a Write cycle is detected,
regardless of the state of OE.
2
, CE
3
are all asserted active. The address presented to A is
Description
X
12. Asserting the Byte Write Enable input
) and ADV inputs are ignored during this
DD
DD
. This pin is not available on
. This pin is not available on
CY7C1480V33
CY7C1482V33
CY7C1486V33
X
) input, will selectively
Truth Table for
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DD
1
X
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