CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet - Page 24

• Manufacturer Part Number: CY7C1480V33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Document Number: 38-05283 Rev. *K
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
Parameter
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
GW, BWE, BW
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
[16, 17]
X
X
Hold After CLK Rise
Setup Before CLK Rise
Description
(continued)
Min
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
250 MHz
Max
–
–
–
–
–
–
–
–
–
–
–
–
Min
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
200 MHz
Max
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1480V33
CY7C1482V33
CY7C1486V33
Min
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
167 MHz
Max
Page 24 of 36
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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