CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet - Page 8

• Manufacturer Part Number: CY7C1480V33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document Number: 38-05283 Rev. *K
Note
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQPs
V
V
V
V
2. Applicable for TQFP package. For BGA package V
Pin Name
0
DD
SS
SSQ
DDQ
, A
1
2
3
A
E
,BW
,BW
1
[2]
, A
B
F
,BW
,BW
G
C
,BW
,BW
H
D
,
IO Power Supply Power supply for the I/O circuitry.
Asynchronous
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
IO Ground
Ground
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O
Address Inputs Used to Select One of the Address Locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
active. A1: A0 are fed to the two-bit counter.
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (all bytes are written, regardless of the values on BW
BWE).
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW during a burst operation.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
HIGH. CE
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQP
Ground for the core of the device.
Ground for the I/O circuitry.
SS
serves as ground for the core and the IO circuitry.
1
is sampled only when a new external address is loaded.
1
1
2
and CE
and CE
and CE
2
3
3
to select or deselect the device. CE
to select or deselect the device. CE
to select or deselect the device. ADSP is ignored if CE
Description
X
are placed in a tri-state condition.
1
, CE
1
is deasserted HIGH.
2
, and CE
3
CY7C1480V33
CY7C1482V33
CY7C1486V33
2
is sampled only when
is sampled only when
3
are sampled
Page 8 of 36
X
and
1
is
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