CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet - Page 25

• Manufacturer Part Number: CY7C1480V33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Read Cycle Timing
Document Number: 38-05283 Rev. *K
Note
Data Out (Q)
22. On this diagram, when CE is LOW: CE
GW, BWE,
ADDRESS
ADSP
ADSC
BWx
ADV
CLK
OE
CE
t
ADS
t AS
t CES
A1
t
ADH
t AH
t CEH
t
[22]
CH
High-Z
t CYC
t WES
t
CL
Single READ
t CLZ
t WEH
t CO
1
t ADS
is LOW, CE
A2
Q(A1)
t ADH
t OEHZ
t ADVS
2
is HIGH and CE
t ADVH
t OELZ
t OEV
Q(A2)
DON’T CARE
t DOH
t CO
3
is LOW. When CE is HIGH: CE
Q(A2 + 1)
ADV
suspends
burst.
UNDEFINED
Q(A2 + 2)
BURST READ
1
is HIGH, CE
Q(A2 + 3)
2
is LOW, or CE
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
3
Q(A2 + 1)
CY7C1480V33
CY7C1482V33
CY7C1486V33
is HIGH.
t CHZ
Deselect
cycle
Page 25 of 36
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