CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet - Page 18

• Manufacturer Part Number: CY7C1480V33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Scan Register Sizes
Identification Codes
Document Number: 38-05283 Rev. *K
Instruction
Bypass
ID
Boundary Scan Order – 165-ball FBGA
Boundary Scan Order – 209-ball BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Register Name
Code
000
001
010
100
101
011
110
111
Captures the IO ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
Do Not Use: This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Bit Size (× 36)
32
73
3
1
–
Description
Bit Size (× 18)
32
54
3
1
–
CY7C1480V33
CY7C1482V33
CY7C1486V33
Bit Size (× 72)
112
32
3
1
–
Page 18 of 36
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