CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet - Page 23

• Manufacturer Part Number: CY7C1480V33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
Document Number: 38-05283 Rev. *K
Notes
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
16. Timing reference level is 1.5V when V
17. Test conditions shown in (a) of
18. This part has an internal voltage regulator; t
19. t
20. At any possible voltage and temperature, t
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
21. This parameter is sampled and not 100% tested.
Parameter
OUTPUT
OUTPUT
can be initiated.
from steady-state voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
CHZ
3.3 V I/O Test Load
2.5 V I/O Test Load
, t
CLZ
,t
OELZ
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low Z
Clock to High Z
OE LOW to Output Valid
OE LOW to Output Low Z
OE HIGH to Output High Z
DD
, and t
Z
Z
0
0
(Typical) to the First Access
= 50 
= 50 
OEHZ
(a)
(a)
are specified with AC test conditions shown in part (b) of
V
V
L
[16, 17]
L
= 1.25 V
AC Test Loads and Waveforms
= 1.5 V
[19, 20, 21]
[19, 20, 21]
R
R
DDQ
L
L
= 50 
= 50 
Description
OEHZ
= 3.3V and is 1.25V when V
POWER
OUTPUT
OUTPUT
[19, 20, 21]
[19, 20, 21]
is less than t
3.3 V
2.5V
is the time that the power needs to be supplied above V
INCLUDING
INCLUDING
[18]
JIG AND
JIG AND
SCOPE
SCOPE
OELZ
5 pF
5 pF
unless otherwise noted.
and t
DDQ
CHZ
(b)
(b)
R = 317 
R = 1667 
= 2.5V.
is less than t
R = 351 
R = 1538 
“AC Test Loads and Waveforms” on page
CLZ
Min
4.0
2.0
2.0
1.3
1.3
1
–
–
–
0
–
250 MHz
to eliminate bus contention between SRAMs when sharing the same
V
GND
GND
V
DDQ
DDQ
Max
3.0
3.0
3.0
3.0
 1 ns
 1 ns
–
–
–
–
–
–
–
DD
10%
10%
(minimum) initially before a read or write operation
Min
5.0
2.0
2.0
1.3
1.3
–
1
–
–
0
–
200 MHz
ALL INPUT PULSES
ALL INPUT PULSES
90%
90%
Max
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
23. Transition is measured ±200 mV
(c)
(c)
CY7C1480V33
CY7C1482V33
CY7C1486V33
Min
6.0
2.4
2.4
1.5
1.5
1
–
–
–
0
–
167 MHz
90%
90%
10%
10%
Max
Page 23 of 36
3.4
3.4
3.4
3.4
–
–
–
–
–
–
–
 1 ns
 1 ns
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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