CY7C1480V33_11 CYPRESS [Cypress Semiconductor], CY7C1480V33_11 Datasheet - Page 10

• Manufacturer Part Number: CY7C1480V33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE
appropriate combination of the Write inputs (GW, BWE, and
BW
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write operations.
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be deasserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a Write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides a
two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
ZZ Mode Electrical Characteristics
Document Number: 38-05283 Rev. *K
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
X
) are asserted active to conduct a Write to the desired
1
, CE
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to Sleep current
ZZ Inactive to exit Sleep current
2
, CE
3
are all asserted active, and (4) the
Description
ZZ > V
ZZ > V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
CE
t
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table
(MODE = GND)
Test Conditions
ZZREC
DD
DD
3
Address
Address
– 0.2 V
, ADSP, and ADSC must remain inactive for the duration of
A1: A0
A1: A0
– 0.2 V
First
First
00
01
10
00
01
10
11
11
after the ZZ input returns LOW.
Address
Address
Second
Second
A1: A0
A1: A0
01
00
10
01
10
00
11
11
2t
Min
CYC
–
–
–
0
DD
Address
Address
)
A1: A0
A1: A0
Third
Third
10
11
00
01
10
11
00
01
CY7C1480V33
CY7C1482V33
CY7C1486V33
2t
2t
Max
120
CYC
CYC
–
–
Page 10 of 36
Address
Address
Fourth
A1: A0
Fourth
A1: A0
Unit
mA
ns
ns
ns
ns
11
10
01
00
11
00
01
10
1
, CE
2
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