CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 9

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Document #: 001-15031 Rev. *H
TDI
TMS
TCK
V
V
V
NC
NC(144M,
288M,
576M, 1G)
ZZ
Pin Name
DD
DDQ
SS
JTAG Serial Input
Test Mode Select
IO Power Supply Power Supply for the IO Circuitry.
Asynchronous
Power Supply
Synchronous
Synchronous
JTAG Clock
IO Type
Ground
Input-
–
–
(continued)
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
This pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Clock Input to the JTAG Circuitry.
Power Supply Inputs to the Core of the Device.
Ground for the Device. Should be connected to ground of the system.
No Connects. This pin is not connected to the die.
These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and
1G densities.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin must be LOW or left floating.
ZZ pin has an internal pull-down.
Pin Description
CY7C1472BV33, CY7C1474BV33
CY7C1470BV33
Page 9 of 33
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