CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 27

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 5
Notes
Document #: 001-15031 Rev. *H
Figure 4
28. For this waveform ZZ is tied LOW.
29. When CE is LOW, CE
30. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A Write is not performed during this cycle.
31. Device must be deselected when entering ZZ mode. See
32. IOs are in High Z when exiting ZZ sleep mode.
In-Out (DQ)
ADDRESS
ADV/LD
BWx
Data
CEN
CLK
WE
shows ZZ Mode timing waveform.
shows NOP, STALL and DESELECT Cycles waveform.
CE
A LL INPUTS
(except ZZ)
Outputs (Q)
WRITE
D(A1)
I
1
A1
SUPPLY
CLK
1
ZZ
is LOW, CE
Q(A2)
READ
A2
2
2
is HIGH, and CE
(continued)
t
ZZI
STALL
t ZZ
I DDZZ
Figure 4. NOP, STALL and DESELECT Cycles
3
[31, 32]
3
is LOW. When CE is HIGH, CE
D(A1)
Truth Table on page 12
Figure 5. ZZ Mode Timing
Q(A3)
READ
A3
4
Q(A2)
WRITE
D(A4)
DON’T CARE
DON’T CARE
A4
5
[28, 29, 30]
High-Z
for all possible signal conditions to deselect the device.
1
STALL
is HIGH, CE
6
Q(A3)
CY7C1472BV33, CY7C1474BV33
2
is LOW or CE
UNDEFINED
NOP
7
DESELECT or READ Only
t RZZI
3
t ZZREC
Q(A5)
D(A4)
READ
is HIGH.
A5
8
DESELECT
CY7C1470BV33
9
CONTINUE
DESELECT
Q(A5)
Page 27 of 33
10
t
CHZ
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