CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 16

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
Document #: 001-15031 Rev. *H
Test M ode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TM S)
(TCK )
(TDI)
1
t TM SS
t TDIS
Figure 2. TAP Timing
2
t TM SH
t TDIH
t TH
DON’T CA RE
t
TL
3
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t CY C
CY7C1472BV33, CY7C1474BV33
UNDEFINED
4
t TDOX
t TDOV
5
6
CY7C1470BV33
Page 16 of 33
[+] Feedback