CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 10

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Functional Overview
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are synchronous-pipelined Burst NoBL SRAMs designed
specifically to eliminate wait states during read or write
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t
Accesses can be initiated by asserting all three Chip Enables
(CE
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). BW
operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
Address Register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus within 3.0 ns (250 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW to drive out the requested
data. During the second clock, a subsequent operation (read,
write, or deselect) can be initiated. Deselecting the device is also
pipelined. Therefore, when the SRAM is deselected at clock rise
by one of the chip enable signals, its output tri-states following
the next clock rise.
Burst Read Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the
Accesses
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
Document #: 001-15031 Rev. *H
1
, CE
3
2
are ALL asserted active, (3) the input signal WE is
, CE
CO
section. The sequence of the burst counter is
) is 3.0 ns (250 MHz device).
3
) active at the rising edge of the clock. If CEN is
[x]
can be used to conduct Byte Write
1
, CE
2
, CE
Single Read
3
) and an
1
, CE
2
,
HIGH input on ADV/LD increments the internal burst counter
regardless of the state of chip enables inputs or WE. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
LOW. The address presented to the address inputs is loaded into
the Address Register. The write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQ
CY7C1472BV33,
CY7C1474BV33). In addition, the address for the subsequent
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQ
CY7C1472BV33,
CY7C1474BV33) (or a subset for byte write operations, see
Partial Write Cycle Description on page 13
latched into the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
BW
CY7C1470BV33,
provides Byte Write capability that is described in
Cycle Description on page
(WE) with the selected BW input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self timed write mechanism
has been provided to simplify the write operations. Byte Write
capability has been included to greatly simplify read, modify, or
write sequences, which can be reduced to simple Byte Write
operations.
Because
CY7C1474BV33 are common IO devices, data must not be
driven into the device while the outputs are active. The OE can
be deasserted HIGH before presenting data to the DQ and DQP
(DQ
CY7C1472BV33,
CY7C1474BV33) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQ
CY7C1470BV33, DQ
DQ
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d
a,b,c,d
a,b,c,d
a,b,c,d
3
are all asserted active, and (3) the signal WE is asserted
CY7C1472BV33, CY7C1474BV33
/DQP
/DQP
/DQP
for CY7C1470BV33, BW
the
/DQP
a,b,c,d
a,b,c,d
a,b,c,d
CY7C1470BV33,
for
a,b,c,d,e,f,g,h
CY7C1472BV33,
and
and
and
for CY7C1470BV33, DQ
for CY7C1470BV33, DQ
for CY7C1470BV33, DQ
a,b
/DQP
CY7C1474BV33)
DQ
DQ
DQ
13. Asserting the Write Enable input
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
a,b
for
a,b
for CY7C1472BV33, and
CY7C1470BV33
for CY7C1472BV33, and
CY7C1472BV33,
CY7C1474BV33)
and
/DQP
/DQP
/DQP
a,b,c,d
for details) inputs is
a,b,c,d,e,f,g,h
a,b,c,d,e,f,g,h
CY7C1474BV33
a,b,c,d,e,f,g,h
signals.
a,b
a,b
a,b
/DQP
Page 10 of 33
/DQP
/DQP
Partial Write
/DQP
a,b,c,d
1
a,b
a,b
a,b
, CE
The
and
are
for
for
for
for
for
for
for
2
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