CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 2

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-15031 Rev. *H
Logic Block Diagram – CY7C1470BV33 (2 M × 36)
Logic Block Diagram – CY7C1472BV33 (4 M × 18)
CLK
CEN
CEN
CLK
A0, A1, A
ADV/LD
A0, A1, A
ADV/LD
MODE
BW
BW
ZZ
C
WE
MODE
CE1
CE2
CE3
BW
BW
OE
BW
BW
C
WE
b
CE1
CE2
CE3
a
OE
ZZ
a
b
c
d
WRITE ADDRESS
WRITE ADDRESS
REGISTER 1
REGISTER 1
REGISTER 0
REGISTER 0
ADDRESS
ADDRESS
Control
CONTROL
READ LOGIC
READ LOGIC
SLEEP
Sleep
AND DATA COHERENCY
AND DATA COHERENCY
WRITE REGISTRY
CONTROL LOGIC
WRITE REGISTRY
CONTROL LOGIC
WRITE ADDRESS
WRITE ADDRESS
ADV/LD
ADV/LD
REGISTER 2
REGISTER 2
C
C
A1
A0
A0
A1
D1
D0
D1
D0
BURST
LOGIC
BURST
LOGIC
Q1
Q0
Q1
Q0
A1'
A0'
A0'
A1'
DRIVERS
WRITE
DRIVERS
WRITE
REGISTER 1
MEMORY
ARRAY
INPUT
MEMORY
CY7C1472BV33, CY7C1474BV33
REGISTER 1
ARRAY
INPUT
E
E
M
E
N
E
A
P
S
S
S
M
E
N
E
A
P
S
S
S
E
O
U
T
P
U
T
R
E
G
T
E
R
E
I
S
S
REGISTER 0
INPUT
REGISTER 0
D
A
A
R
N
G
T
S
T
E
E
I
INPUT
D
A
A
R
N
G
T
S
T
E
E
I
E
E
O
U
T
P
U
T
B
U
F
F
E
R
S
E
O
U
U
B
U
R
T
P
T
F
F
E
S
E
CY7C1470BV33
DQ s
DQ P
DQ P
DQ P
DQ P
a
b
c
d
DQ s
DQ P
DQ P
a
b
Page 2 of 33
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