CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 11

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

load the initial address, as described in
on page
clock rise, the Chip Enables (CE
are ignored and the burst counter is incremented. The correct
BW (BW
and BW
in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Document #: 001-15031 Rev. *H
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
3
a,b,c,d,e,f,g,h
, must remain inactive for the duration of t
a,b,c,d
10. When ADV/LD is driven HIGH on the subsequent
for CY7C1470BV33, BW
for CY7C1474BV33) inputs must be driven
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
1
, CE
Description
2
, and CE
a,b
Single Write Accesses
for CY7C1472BV33,
3
) and WE inputs
ZZREC
after the
1
, CE
ZZ  V
ZZV
ZZ  0.2 V
This parameter is sampled
This parameter is sampled
2
,
Interleaved Burst Address Table
(MODE = Floating or V
Linear Burst Address Table (MODE = GND)
DD
DD
 0.2 V
 0.2 V
Address
Test Conditions
Address
A1, A0
A1, A0
First
First
00
01
10
11
00
01
10
11
CY7C1472BV33, CY7C1474BV33
Address
Second
Address
Second
A1, A0
A1, A0
01
00
11
10
01
10
00
11
DD
2t
Min
)
Address
Address
CYC
A1, A0
–
–
–
0
A1, A0
CY7C1470BV33
Third
Third
10
00
01
11
10
00
01
11
2t
2t
Max
120
CYC
CYC
–
–
Page 11 of 33
Address
Address
Fourth
A1, A0
Fourth
A1, A0
11
10
01
00
11
00
01
10
Unit
mA
ns
ns
ns
ns
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