CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 13

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Partial Write Cycle Description
The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.
Document #: 001-15031 Rev. *H
Read
Write – No bytes written
Write Byte a – (DQ
Write Byte b – (DQ
Write Bytes b, a
Write Byte c – (DQ
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQ
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
Read
Write – No Bytes Written
Write Byte a – (DQ
Write Byte b – (DQ
Write Both Bytes
Read
Write – No Bytes Written
Write Byte X(DQ
Write All Bytes
Notes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
9. Write is defined by WE and BW
10. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
11. Table lists only a partial listing of the Byte Write combinations. Any combination of BW
signifies that the desired byte write selects are asserted, see
Function (CY7C1470BV33)
Function (CY7C1472BV33)
Function (CY7C1474BV33)
c
a
b
d
a
b
x
and DQP
and DQP
and DQP
and DQP
and DQP
and DQP
and DQP
[a:d]
c
a
d
a
b
x)
b
)
)
)
)
)
. See
)
Partial Write Cycle Description on page 13
Partial Write Cycle Description on page 13
WE
WE
WE
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
for details.
[a:d]
BW
is valid. Appropriate Write is based on which Byte Write is active.
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
CY7C1472BV33, CY7C1474BV33
d
BW
H
H
L
L
x
b
for details.
BW
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
c
All BW = L
BW
H
x
L
x
[8, 9, 10, 11]
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
CY7C1470BV33
b
BW
H
H
L
x
L
a
Page 13 of 33
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
a
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