CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 3

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CY7C1470BV33_11

Manufacturer Part Number
CY7C1470BV33_11
Description
72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Document #: 001-15031 Rev. *H
Logic Block Diagram – CY7C1474BV33 (1 M × 72)
CEN
CLK
A0, A1, A
ADV/LD
MODE
BW
BW
BW
BW
BW
BW
BW
BW
ZZ
C
WE
CE1
CE2
CE3
OE
a
b
c
e
f
h
d
g
WRITE ADDRESS
REGISTER 1
REGISTER 0
ADDRESS
Control
READ LOGIC
Sleep
AND DATA COHERENCY
WRITE REGISTRY
CONTROL LOGIC
WRITE ADDRESS
ADV/LD
REGISTER 2
C
A0
A1
D1
D0
BURST
LOGIC
Q1
Q0
A0'
A1'
DRIVERS
WRITE
MEMORY
REGISTER 1
ARRAY
INPUT
CY7C1472BV33, CY7C1474BV33
E
M
S
E
N
S
E
A
P
S
O
U
T
P
U
T
R
E
G
T
E
R
E
I
S
S
REGISTER 0
INPUT
D
A
A
N
G
T
S
T
E
E
R
I
E
O
U
U
U
T
P
T
B
F
F
E
R
S
E
CY7C1470BV33
DQ s
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
DQ P
a
b
c
d
e
f
g
h
Page 3 of 33
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