CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 25

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Notes
Document #: 001-15031 Rev. *H
19. Timing reference is 1.5 V when V
20. Test conditions shown in (a) of
21. This part has an internal voltage regulator; t
22. t
23. At any voltage and temperature, t
24. This parameter is sampled and not 100% tested.
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Power
CYC
CH
CL
CO
OEV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
MAX
steady-state voltage.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
CHZ
Parameter
[21]
, t
CLZ
, t
EOLZ
, and t
V
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High Z
Clock to Low Z
OE HIGH to Output High Z
OE LOW to Output Low Z
Address Setup Before CLK Rise
Data Input Setup Before CLK Rise
CEN Setup Before CLK Rise
WE, BW
ADV/LD Setup Before CLK Rise
Chip Select Setup
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
EOHZ
CC
are specified with AC test conditions shown in (b) of
(typical) to the First Access Read or Write
[19, 20]
AC Test Loads and Waveforms on page 24
x
x
DDQ
EOHZ
Setup Before CLK Rise
Hold After CLK Rise
= 3.3 V and is 1.25 V when V
is less than t
[22, 23, 24]
[22, 23, 24]
power
Description
is the time power is supplied above V
EOLZ
[22, 23, 24]
[22, 23, 24]
and t
CHZ
is less than t
DDQ
= 2.5 V.
unless otherwise noted.
CLZ
AC Test Loads and Waveforms on page
to eliminate bus contention between SRAMs when sharing the same data bus.
DD
Min
4.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
–
–
0
minimum initially, before a read or write operation can be initiated.
-250
CY7C1472BV33, CY7C1474BV33
Max
250
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
–
–
–
–
–
0
-200
24. Transition is measured ±200 mV from
Max
200
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CY7C1470BV33
Min
6.0
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
–
–
–
0
-167
Max
Page 25 of 33
167
3.4
3.4
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
MHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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