CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 26

• Manufacturer Part Number: CY7C1470BV33_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Figure 3
Notes
Document #: 001-15031 Rev. *H
25. For this waveform ZZ is tied LOW.
26. When CE is LOW, CE
27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
In-Out (DQ)
ADDRESS
ADV/LD
shows read-write timing waveform.
Data
CEN
BW
CLK
WE
OE
CE
x
t
t
t
CENS
AS
CES
WRITE
D(A1)
A1
1
1
is LOW, CE
t
t
CENH
t
AH
CEH
WRITE
D(A2)
2
2
is HIGH, and CE
A2
t
CH
t CYC
t
t
DS
CL
D(A2+1)
BURST
WRITE
D(A1)
3
[25, 26, 27]
t
DH
3
is LOW. When CE is HIGH, CE
Figure 3. Read/Write Timing
DON’T CARE
D(A2)
READ
Q(A3)
A3
4
D(A2+1)
READ
Q(A4)
A4
5
t
t
CO
CLZ
UNDEFINED
1
is HIGH, CE
Q(A4+1)
BURST
READ
Q(A3)
6
t
DOH
CY7C1472BV33, CY7C1474BV33
t
OEHZ
2
is LOW or CE
WRITE
D(A5)
Q(A4)
A5
7
t
OEV
t
OELZ
3
Q(A6)
is HIGH.
Q(A4+1)
READ
A6
8
t
t
DOH
CHZ
CY7C1470BV33
WRITE
D(A7)
9
D(A5)
A7
DESELECT
Page 26 of 33
10
Q(A6)
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