CY7C1470BV33_11 CYPRESS [Cypress Semiconductor], CY7C1470BV33_11 Datasheet - Page 23

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CY7C1470BV33_11

Manufacturer Part Number
CY7C1470BV33_11
Description
72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Electrical Characteristics (continued)
Over the Operating Range
Note
Document #: 001-15031 Rev. *H
I
I
I
I
I
18. The operation current is calculated with 50% read cycle and 50% write cycle.
DD
SB1
SB2
SB3
SB4
Parameter
[18]
V
Automatic CE
Power Down
Current—TTL Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—CMOS Inputs
Automatic CE
Power Down
Current—TTL Inputs
DD
Operating Supply
Description
[16, 17]
V
f = f
Max V
V
f = f
Max V
V
f = 0
Max V
V
f = f
Max V
V
DD
IN
IN
IN
IN
MAX
 V
MAX
 0.3 V or V
 0.3 V or V
MAX
 V
= Max, I
DD
DD
DD
DD
IH
IH
= 1/t
= 1/t
= 1/t
, Device Deselected,
, Device Deselected,
, Device Deselected,
, Device Deselected,
or V
or V
OUT
CYC
CYC
CYC
IN
IN
IN
IN
 V
 V
= 0 mA,
> V
> V
IL
IL
Test Conditions
DDQ
DDQ
,
, f = 0
0.3 V,
0.3 V,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
CY7C1472BV33, CY7C1474BV33
Min
CY7C1470BV33
Max
500
500
450
245
245
245
120
245
245
245
135
Page 23 of 33
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
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