PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 91

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
Note:
Table 40: BEFP Requirements and Considerations
9.6.3.1
Caution:
9.6.3.2
April 2008
309823-10
BEFP Considerations
BEFP Requirements
Section 6.0, “Flow Charts” on page 41
Table 40, “BEFP Requirements and Considerations” on page 91
requirements and considerations.
For BEFP voltage and temperature operating restrictions, see the datasheet. The block
erase cycles in
for optimal performance. If exceeded some degradation in performance may occur;
however, the internal algorithm will still function correctly.
Setup Phase
Issuing the BEFP Setup and Confirm command sequence starts the BEFP algorithm. The
read mode of the addressed partition is automatically changed to Read Status Register
mode.
The address used when issuing the setup/confirm commands must be buffer-size
aligned within the block being programmed -- buffer contents cannot cross block
boundaries.
The Read Status Register command must not be issued -- it will be interpreted
as data to be written to the write buffer.
A setup delay (t
status. If errors are detected, the appropriate Status Register error bits are set and the
operation aborts.
The Status Register should be polled for successful BEFP setup, indicated by SR[7,0] =
0 (Device Busy, Buffer Ready for Data).
Program/Verify Phase
Data is first written into the write buffer, then programmed into the flash array. During
the buffer-fill sequence, the address used must be buffer-size aligned. Use of any other
address will cause the operation to abort with a program fail error, and any data
previously loaded in the buffer will not be programmed into the array.
The buffer-fill data is stored in sequential buffer locations starting at address 00h. A
word count equal to the maximum buffer size is used, therefore, the buffer must be
completely filled. If the amount of data is less than the maximum buffer size, the
remaining buffer locations must be “padded” with FFFFh to completely fill the buffer.
Flash array programming starts as soon as the write buffer is full. Data words from the
write buffer are programmed into sequential array locations. SR0 = 1 indicates the
write buffer is not available while the BEFP algorithm programs the array.
®
Cellular Memory (M18)
Table 40, “BEFP Requirements and Considerations”
BEFP/Setup
Temperature (T
Voltage on V
Voltage on VPP must be within the allowable operating range
Block being programmed must be erased and unlocked
Block cycling below 100 erase cycles
Reading from another partition during EFP (RWW) is not allowed
BEFP programs within one block at a time
BEFP cannot be suspended
) occurs while the internal algorithm checks V
CC
CASE
must be within the allowable operating range
) must be 25 °C, ± 5 °C
contains a flow chart of the BEFP operation.
lists specific BEFP
are recommended
PP
and block-lock
Datasheet
91