PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 90

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Note:
Note:
9.6.3
Datasheet
90
Following the word count, subsequent bus-write cycles fill the write buffer with user-
data up to the word count.
User-data is programmed into the flash array at the address issued when filling the
write buffer.
The Confirm command (00D0h) is issued after all user-data is written into the write
buffer. The read mode of the device/addressed partition is automatically changed to
Read Status Register mode. If other than the Confirm command is issued to the device,
a command sequence error occurs and the operation aborts.
After the Confirm command has been issued, the write-buffer contents are
programmed into the flash memory array. The Status Register indicates a busy status
(SR7 = 0) during array programming.
During array programming, the only valid commands are Read Array, Read Device
Information, CFI Query, Read Status, and Program Suspend. After array programming
has completed (SR7 = 1), any valid command can be issued. Reading from another
partition is allowed while data is being programmed into the flash memory array from
the write buffer.
Issuing the Read Array, Read Device Information, or CFI Query command to a partition
that is actively programming or erasing causes subsequent reads from that partition to
output invalid data. Valid data is output only after the program or erase operation has
finished.
Upon completion of array programming, the Status Register indicates ready (SR7 =
1b). A full Status Register check should be performed to check for any programming
errors. Then the Status Register should be cleared using the Clear Status Register
command.
A subsequent buffered programming operation can be initiated by repeating the
buffered programming sequence. Any errors in the Status Register caused by the
previous operation must be cleared to prevent them from masking any errors that may
occur during the subsequent operation.
Buffered Enhanced Factory Programming (BEFP)
Buffered Enhanced Factory Programming (BEFP) improves programming performance
through the use of the write buffer, elevated programming voltage (V
enhanced programming algorithm. User-data is written into the write buffer, then the
buffer contents are automatically written into the flash array in buffer-size increments.
BEFP is allowed in both Control Mode and Object Mode. The programming mode
selection for the entire flash array block is driven by the specific type of information,
such as header or object data. Header/object data is aligned on a 1 KB programming
region boundary in the main array block.
Internal verification during programming (inherent to MLC technology) and Status
Register error checking are used to determine proper completion of the programming
operation. This eliminates delays incurred when switching between single-word
program and verify operations.
BEFP consists of three distinct phases:
1. Setup Phase: V
2. Program/Verify Phase: buffered programming and verification
3. Exit Phase: block-error check
PPH
and block-lock checks
Numonyx™ StrataFlash
®
Cellular Memory (M18)
PPH
), and
309823-10
April 2008