PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 50

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Table 19: AC Read, 108 MHz, V
Datasheet
50
Asynchronous Specifications
Latching Specifications
Clock Specifications
Synchronous Specifications
R101
R102
R103
R104
R105
R106
R107
R108
R111
R200
R201
R202
R203
R301
R302
Nbr.
R10
R11
R12
R13
R14
R15
R16
R17
R1
R2
R3
R4
R5
R6
R7
R8
R9
t
Symbol
FCLK/RCLK
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CH/CL
GHQZ
t
t
AVQV
GLQV
PHQV
GLQX
EHQZ
GHTV
GHTZ
AVVH
VHAX
VHGL
PHVH
f
AVCH
AVAV
ELQV
ELQX
EHEL
EHTZ
GLTV
GLTX
ELVH
VLQV
VLVH
VHVL
VLCH
t
ELTV
CLK
APA
CLK
OH
Read cycle time
Address to output valid
CE# low to output valid
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
CE# low to WAIT valid
CE# high to WAIT high Z
OE# high to WAIT valid (AD-Mux only)
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# low to WAIT in high-Z (non-mux only)
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
ADV# high to OE# low (AD-Mux only)
Page address access (non-mux only)
RST# high to ADV# high
CLK frequency
CLK period
CLK high/low time
CLK fall/rise time
Address setup to CLK high
ADV# low setup to CLK high
CCQ
= 1.7 V to 2.0 V (Sheet 1 of 2)
Parameter
1
Numonyx™ StrataFlash
9.26
0.45
Min
0.3
96
30
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
7
0
0
5
9
7
7
5
7
5
5
96 ns
®
Max
0.55
150
108
1.2
96
96
20
11
96
15
Cellular Memory (M18)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
9
9
7
7
9
period
Unit
MHz
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
309823-10
April 2008
Notes
2,3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
3
3
3
3
4