PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 28

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Table 7:
Datasheet
28
OE#
F-RST#
F-WAIT
WE#
D-WE#
F-
WP[2:1]#
F-DPD
N-CLE
N-ALE
N-RE#
N-RY/BY#
N-WE#
D-CKE
D-BA[1:0]
D-RAS#
D-CAS#
D[2:1]-
CS#
Symbol
Output
Output
Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 3 of 4)
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
OUTPUT ENABLE: Flash- and SRAM-specific signal; low-true input.
When low, OE# enables the output drivers of the selected flash or SRAM die. When high, OE#
disables the output drivers of the selected flash or SRAM die and places the output drivers in
High-Z.
FLASH RESET: Flash-specific signal; low-true input.
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
FLASH WAIT: Flash -specific signal; configurable-true output.
When asserted, F-WAIT indicates invalid output data. F-WAIT is driven whenever F-CE# and
OE# are low. F-WAIT is High-Z whenever F-CE# or OE# is high.
WRITE ENABLE: Flash- and SRAM-specific signal; low-true input.
When low, WE# enables Write operations for the enabled flash or SRAM die.
LPSDRAM WRITE ENABLE: LPSDRAM-specific signal; low-true input.
D-WE#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-RAS#, define the
LPSDRAM command or operation. D-WE# is sampled on the rising edge of D-CLK.
FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.
When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-
Down function, enabling locked-down blocks to be unlocked with the Unlock command.
FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input.
When enabled in the ECR, F-DPD is used to enter and exit Deep Power-Down mode.
NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-CLE enables commands to be latched on the rising edge of N-WE#.
NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.
When high, N-ALE enables addresses to be latched on the rising edge of N-WE#.
NAND READ ENABLE: NAND-specific signal; low-true input.
When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE#
disables the output drivers of the selected NAND die and places the output drivers in High-Z.
NAND READY/BUSY: NAND-specific signal; low-true output.
When low, N-RY/BY# indicates the NAND is busy performing a read, program, or erase
operation. When high, N-RY/BY# indicates the NAND device is ready.
NAND WRITE ENABLE: NAND-specific signal; low-true input.
When low, N-WE# enables Write operations for the enabled NAND die.
LPSDRAM CLOCK ENABLE: LPSDRAM-specific signal; high-true input.
When high, D-CKE indicates that the next D-CLK edge is valid. When low, D-CKE indicates that
the next D-CLK edge is invalid and the selected LPSDRAM die is suspended.
LPSDRAM BANK SELECT: LPSDRAM-specific input signals.
D-BA[1:0] selects one of four banks in the LPSDRAM die.
LPSDRAM ROW ADDRESS STROBE: LPSDRAM-specific signal; low-true input.
D-RAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-WE#, define the
LPSDRAM command or operation. D-RAS# is sampled on the rising edge of D-CLK.
LPSDRAM COLUMN ADDRESS STROBE: LPSDRAM-specific signal; low-true input.
D-CAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-RAS#, and D-WE#, define the
LPSDRAM command or operation. D-CAS# is sampled on the rising edge of D-CLK.
LPSDRAM CHIP SELECT: LPSDRAM-specific signal; low-true input.
When low, D-CS# selects the associated LPSDRAM memory die and starts the command input
cycle. When D-CS# is high, commands are ignored but operations continue.
• F-WP1# is dedicated to flash die #1.
• F-WP2# is common to all other flash dies, if present. Otherwise it is RFU.
• For NOR/NAND stacked device, F-WP1# selects all NOR dies; F-WP2# selects all NAND dies.
• D-CS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-RAS#, D-CAS#, and D-WE#, define
• D[2:1]-CS# are dedicated to LPSDRAM die #2 and die #1, respectively, if present.
the LPSDRAM command or operation. D-CS# is sampled on the rising edge of D-CLK.
Otherwise, any unused LPSDRAM chip selects should be treated as RFU.
Signal Descriptions
Numonyx™ StrataFlash
®
Cellular Memory (M18)
309823-10
April 2008
Notes
2, 4
2, 5
2
2
2
2
2
2
2
2
2