h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 414

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h8s-2111b

Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Table 15.2 Register Selection
15.3.4
The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit write-
only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on IDR3 selection, see section 15.3.3,
LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written
to the selected register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to
indicate whether the written information is a command or data. The initial values of IDR1 to IDR3
are undefined.
Rev. 1.00, 05/04, page 380 of 544
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bits 15 to 4
0000 0000 0110
0000 0000 0110
0000 0000 0110
0000 0000 0110
Input Data Registers 1 to 3 (IDR1 to IDR3)
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
0
0
1
0
0
1
I/O Address
Bit 2
0
1
0
1
0
0
1
0
0
1
I/O Address
Bit 3
0
0
0
0
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
0
0
1
0
0
1
Bit 2
0
1
0
1
Bit 0
0
0
0
0
0
1
1
0
1
1
Bit 1
0
0
1
1
Bit 0
0
0
0
0
Transfer
Cycle
I/O read
I/O write
I/O read
I/O write
I/O write
I/O read
I/O write
I/O read
Transfer
Cycle
I/O write
I/O write
I/O write
I/O write
Host Register Selection
IDR3 write, C/D3 ← 0
IDR3 write, C/D3 ← 1
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15 write
TWR0SW read
TWR1 to TWR15 read
Host Register Selection
IDR1 write, C/D1 ← 0
IDR1 write, C/D1 ← 1
IDR2 write, C/D2 ← 0
IDR2 write, C/D2 ← 1

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