h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 110

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

5.4
5.4.1
There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to
WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0
share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6 , and IRQ2 to IRQ0 can be used to
restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• Interrupt control levels can be specified by the ICR settings.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, do not clear
the corresponding DDR to 0 to use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.
When pin IRQ6 is used as an IRQ6 interrupt input pin, clear the KMIMR6 bit to 0.
Rev. 1.00, 05/04, page 76 of 544
independent vector address.
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
by software.
Interrupt Sources
IRQn input
External Interrupts
n = 7 to 0
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0
IRQnSCA, IRQnSCB
detection circuit
Edge/level
Clear signal
R
S
IRQnF
Q
IRQnE
IRQn interrupt
request