h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 27

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 13.25 IRIC Setting Timing and SCL Control (1) ............................................................ 331
Figure 13.26 IRIC Setting Timing and SCL Control (2) ............................................................ 332
Figure 13.27 IRIC Setting Timing and SCL Control (3) ............................................................ 333
Figure 13.28 Block Diagram of Noise Canceler......................................................................... 334
Figure 13.29 Notes on Reading Master Receive Data ................................................................ 340
Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission
and Timing............................................................................................................. 341
Figure 13.31 Stop Condition Issuance Timing ........................................................................... 342
Figure 13.32 IRIC Flag Clearing Timing when WAIT = 1 ........................................................ 343
Figure 13.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 344
Figure 13.34 TRS Bit Set Timing in Slave Mode....................................................................... 345
Figure 13.35 Diagram of Erroneous Operation when Arbitration is Lost................................... 347
Section 14 Keyboard Buffer Controller
Figure 14.1 Block Diagram of Keyboard Buffer Controller....................................................... 349
Figure 14.2 Keyboard Buffer Controller Connection ................................................................. 350
Figure 14.3 Sample Receive Processing Flowchart.................................................................... 355
Figure 14.4 Receive Timing ....................................................................................................... 356
Figure 14.5 Sample Transmit Processing Flowchart (1)............................................................ 357
Figure 14.5 Sample Transmit Processing Flowchart (2)............................................................. 358
Figure 14.6 Transmit Timing...................................................................................................... 358
Figure 14.7 Sample Receive Abort Processing Flowchart (1) ................................................... 359
Figure 14.7 Sample Receive Abort Processing Flowchart (2) ................................................... 360
Figure 14.8 Receive Abort and Transmit Start
(Transmission/Reception Switchover) Timing ....................................................... 360
Figure 14.9 KCLKI and KDI Read Timing ................................................................................ 361
Figure 14.10 KCLKO and KDO Write Timing .......................................................................... 361
Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing ..................... 362
Figure 14.12 Receive Counter and KBBR Data Load Timing ................................................... 363
Figure 14.13 Example of KCLK Input Fall Interrupt Operation ................................................ 364
Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing ................................. 365
Section 15 Host Interface (LPC)
Figure 15.1 Block Diagram of LPC............................................................................................ 370
Figure 15.2 Typical LFRAME Timing....................................................................................... 400
Figure 15.3 Abort Mechanism .................................................................................................... 400
Figure 15.4 GA20 Output ........................................................................................................... 401
Figure 15.5 Power-Down State Termination Timing ................................................................. 406
Figure 15.6 SERIRQ Timing ...................................................................................................... 407
Figure 15.7 Clock Start Request Timing .................................................................................... 409
Figure 15.8 HIRQ Flowchart (Example of Channel 1)............................................................... 412
Rev. 1.00, 05/04, page xxvii of xxxiv