h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 323

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h8s-2111b

Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
13.3.5
ICCR controls the I
Bit
7
6
5
4
Bit Name
ICE
IEIC
MST
TRS
I
2
C Bus Control Register (ICCR)
2
C bus interface and performs interrupt flag confirmation.
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I
0: I
1: I
I
0: Disables interrupts from the I
1: Enables interrupts from the I
Master/Slave Select
Transmit/Receive Select
MST
0
0
1
1
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode with the I
format. In slave receive mode with I
R/W bit in the first frame immediately after the start
condition sets these bits in receive mode or transmit
mode automatically by hardware.
Modification of the TRS bit during transfer is deferred
until transfer is completed, and the changeover is made
after completion of the transfer.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
interface module internal state is initialized. SAR and
SARX can be accessed.
operation, and the ports function as the SCL and SDA
input/output pins. ICMR and ICDR can be accessed.
CPU
CPU.
2
2
C bus interface modules are stopped and I
C bus interface modules can perform transfer
TRS
0
1
0
1
: Slave receive mode
: Slave transmit mode
: Master receive mode
: Master transmit mode
Rev. 1.00, 05/04, page 289 of 544
2
2
C bus interface to the
C bus interface to the
2
C bus format, the
2
C bus
2
C bus

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