h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 327
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h8s-2111b
Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2111B.pdf
(582 pages)
- Current page: 327 of 582
- Download datasheet (4Mb)
Note:
When, with the I
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag is not
set at the end of a data transfer up to detection of a retransmission start condition or stop condition
after a slave address (SVA) or general call address match in I
Tables 13.4 and 13.5 show the relationship between the flags and the transfer states.
Bit
1
*
Bit Name
IRIC
Only 0 can be written, to clear the flag.
2
C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
Initial
Value
0
R/W
R/(W)*
Description
Clocked synchronous serial format mode:
•
•
When the ICDRE or ICDRF flag is set to 1 in any
operating mode:
•
•
[Clearing conditions]
•
At the end of data transfer (rise of the 8th
transmit/receive)
When a start condition is detected
When a start condition is detected in transmit mode
(when a start condition is detected in transmit mode
and the ICDRE flag is set to 1)
When data is transferred among ICDR and buffer
(when data is transferred from ICDRT to ICDRS in
transmit mode and the ICDRE flag is set to 1, or
when data is transferred from ICDRS to ICDRR in
receive mode and the ICDRF flag is set to 1)
When 0 is written in IRIC after reading IRIC = 1
2
C bus format slave mode.
Rev. 1.00, 05/04, page 293 of 544
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