h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 381

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Note:
13.6.1
The IIC operation can be enabled or disabled using the module stop control register. The initial
setting is for the IIC operation to be halted. Register access is enabled by canceling module stop
mode. For details, see section 20, Power-Down Modes.
(Master transmit mode)
(Master transmit mode)
(Slave receive mode)
I
I
Though it is prohibited in the normal I
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
B. Set the MST bit to 1.
C. To confirm that the bus was not entered to the busy state while the MST bit is being set,
2
2
C bus interface
C bus interface
Other device
the MST bit.
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Above restriction can be cleared by setting bits FNC1 and FNC0 in the ICXR register.
Module Stop Mode Setting
Figure 13.35 Diagram of Erroneous Operation when Arbitration is Lost
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
2
C protocol, the same problem may occur when the MST
A
A
A
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as an
• When the receive data matches to
receive mode
address
the address set in the SAR or SARX
register, the I
as a slave device.
SLA
DATA1
DATA2
2
C bus interface operates
Transmit data does not match
R/W
Rev. 1.00, 05/04, page 347 of 544
A
A
DATA4
DATA3
Data contention
A
A