h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 278
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h8s-2111b
Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2111B.pdf
(582 pages)
- Current page: 278 of 582
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12.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 12.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 12.2 Relationships between N Setting in BRR and Bit Rate B
[Legend]
B:
N:
φ:
n:
Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the
maximum bit rate settable for each frequency. Table 12.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 12.5 and 12.7 show the maximum bit rates with external clock
input.
Rev. 1.00, 05/04, page 244 of 544
Mode
Asynchronous mode
Clocked synchronous
mode
CKS1
0
0
1
1
SMR Setting
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table.
Bit Rate Register (BRR)
CKS0
0
1
0
1
n
0
1
2
3
Bit Rate
B =
B =
64 × 2
64 × 2
φ × 10
φ × 10
2n-1
2n-1
× (N + 1)
× (N + 1)
6
6
Error
Error (%) = {
—
B × 64 × 2
φ × 10
2n-1
6
× (N + 1)
- 1 } × 100
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