ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 99

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
10.4.6
Note:
Caution:
10.4.7
10.4.8
Low power modes
Table 52.
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. Therefore,
if Slave selection is configured as external (see
make sure the master drives a low level on the SS pin when the slave enters Halt mode.
Interrupts
Table 53.
1. The SPI interrupt events are connected to the same interrupt vector (see
SPI registers
SPI Control Register (SPICR)
SPI end of transfer event
Master mode fault event
Overrun error
SPICR
Mode
Wait
Halt
generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC
register is reset (RIM instruction).
SPIE
R/W
Interrupt event
7
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an
interrupt with Exit from Halt mode capability. The data received is subsequently read from
the SPIDR register when the software is running (interrupt vector fetching). If several data
are received before the wake-up event, then an overrun error is generated. This error can
be detected after the fetch of the interrupt routine that woke up the device.
Effect of low power modes on SPI
SPI interrupt control/wake-up capability
SPE
R/W
6
SPR2
R/W
Event flag
5
MODF
SPIF
OVR
MSTR
R/W
4
Enable control bit
Description
SPIE
Slave Select management on page
CPOL
R/W
3
(1)
Exit from WAIT Exit from HALT
CPHA
R/W
Section 7:
2
Reset value: 0000 xxxx (0xh)
Yes
On-chip peripherals
Interrupts). They
1
SPR[1:0]
R/W
Yes
No
93),
0
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