ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 92

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

On-chip peripherals
10.4.3
92/188
General description
Figure 50
registers:
The SPI is connected to external devices through four pins:
Figure 50. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
MOSI
MISO
SCK
SS
–
–
–
–
–
–
–
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
MISO: Master In / Slave Out data
MOSI: Master Out / Slave In data
SCK: Serial Clock out by SPI masters and input by SPI slaves
SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines.
Slave SS inputs can be driven by standard I/O ports on the master MCU.
shows the serial peripheral interface (SPI) block diagram. The SPI has three
SOD
Figure
bit
SPIDR
51.
8-bit Shift Register
Read Buffer
Serial clock
generator
Master
control
Data/Address bus
Read
Write
7
SPIF WCOL
SPIE SPE
7
SPR2
OVR
control
state
SPI
Interrupt
request
MODF
MSTR
CPOL
0
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
ST72324B
1
0
SPR0
SSI
0
0