ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 79

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
One Pulse mode
One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use One Pulse mode:
1.
2.
3.
Figure 46. One pulse mode cycle
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
Load the OC1R register with the value corresponding to the length of the pulse (see the
formula below).
Select the following in the CR1 register:
–
–
–
Select the following in the CR2 register:
–
–
–
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiLR register.
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
Set the OPM bit.
Select the timer clock CC[1:0] (see
event occurs
on ICAP1
counter =
When
When
OC1R
Table
OCMP1 = OLVL2
OCMP1 = OLVL1
Counter is reset
ICR1 = Counter
ICF1 bit is set
to FFFCh
49).
On-chip peripherals
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