ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 39

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
Note:
7.3
Note:
7.4
peripheral control register. The general sequence for clearing an interrupt is based on an
access to the status register followed by a read or write to an associated register.
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) is therefore lost if the clear sequence is executed.
Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column Exit from HALT in
present while exiting Halt mode, the first one serviced can only be an interrupt with Exit from
Halt mode capability and it is selected through the same decision process shown in
Figure
If an interrupt, that is not able to exit from Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced after the first one serviced.
Concurrent and nested management
Figure 20
concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode
in
as follows: MAIN, IT4, IT3, IT2, IT1, IT0. Software priority is given for each interrupt.
Figure 20. Concurrent interrupt management
Figure
Warning:
19.
21. The interrupt hardware priority is given in order from the lowest to the highest
and
Figure 21
11/10
Main
RIM
A stack overflow may occur without notifying the software of
the failure.
IT2
show two different interrupt management modes. The first is called
Table 24: Interrupt
IT1
TRAP
IT1
IT0
mapping). When several pending interrupts are
IT3
IT4
10
Software
priority
level
Main
3
3
3
3
3
3
3/0
I1
1 1
1 1
1 1
1 1
1 1
1 1
Interrupts
I0
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