ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 101

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
Table 55.
SPI Control/Status Register (SPICSR)
Table 56.
SPICSR
Bit
7
6
5
4
3
SPIF
RO
7
WCOL
MODF
Name
SPIF
OVR
-
SPI master mode SCK frequency (continued)
SPICSR register description
Serial Peripheral data transfer flag
Write Collision status
SPI Overrun error
Mode Fault flag
Reserved, must be kept cleared.
WCOL
Serial clock
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see
0: No write collision occurred
1: A write collision has been detected.
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see
condition (OVR) on page
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault (MODF) on page
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
0: No master mode fault detected
1: A fault in master mode has been detected.
RO
6
f
f
f
f
CPU
CPU
CPU
CPU
/128
/16
/32
/64
OVR
RO
5
MODF
97). An interrupt is generated if SPIE = 1 in SPICR
RO
4
SPR2
Reserved
Function
97). An SPI interrupt can be generated if
0
1
0
0
3
-
SOD
R/W
2
SPR1
Reset value: 0000 0000 (00h)
0
1
1
1
On-chip peripherals
Figure
SSM
R/W
1
55).
Overrun
SPR0
1
0
0
1
R/W
SSI
101/188
0