ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 31

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
Figure 15. RESET sequences
6.5
6.5.1
RESET pin
Watchdog
reset
External
RESET
source
V
V
IT+(LVD)
IT-(LVD)
System integrity management (SI)
The system integrity management block contains the LVD and auxiliary voltage detector
(AVD) functions. It is managed by the SICSR register.
LVD (low voltage detector)
The LVD function generates a static reset when the V
reference value. This means that it secures the power-up as well as the power-down
keeping the ST7 in reset.
The V
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when V
The LVD function is illustrated in
The voltage threshold can be configured by option byte to be low, medium or high.
–
–
IT-
V
Run
DD
reference value for a voltage drop is lower than the V
V
V
IT+
IT-
when V
when V
Active phase
reset
LVD
DD
DD
is falling
is rising
t
h(RSTL)in
Figure
Run
15.
Watchdog underflow
phase
Active
External
reset
DD
Supply, reset and clock management
is below:
DD
Internal reset (256 or 4096 T
Vector fetch
Run
supply voltage is below a V
IT+
Active
phase
Watchdog
t
w(RSTL)out
reset
reference value for power-
Run
CPU
)
IT-
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