ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 95

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
Note:
Note:
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
–
–
An access to the SPICSR register while the SPIF bit is set.
A read to the SPIDR register.
Write to the SPICSR register to perform the following actions:
–
–
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
–
–
An access to the SPICSR register while the SPIF bit is set.
A write or a read to the SPIDR register.
The SPIF bit is set by hardware
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see
master.
Manage the SS pin as described in
Figure
be held low during byte transmission and pulled up between each byte to let the
slave write in the shift register.
The SPIF bit is set by hardware
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Figure
52. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must
54). The slave must have the same CPOL and CPHA settings as the
Slave Select management on page 93
On-chip peripherals
and
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