ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 47

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ST72F324BJ

Manufacturer Part Number
ST72F324BJ
Description
8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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ST72324B
8
8.1
8.2
Note:
Power saving modes
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see
Wait), Active Halt and Halt.
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 23. Power saving mode transitions
Slow mode
This mode has two targets:
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (f
In this mode, the master clock frequency (f
and peripherals are clocked at this lower frequency (f
Slow-Wait mode is activated when entering the Wait mode while the device is already in
Slow mode.
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f
Power consumption
Active Halt
Slow Wait
OSC2
CPU
Slow
Wait
Run
Halt
) to the available supply voltage.
) can be divided by 2, 4, 8 or 16. The CPU
Low
High
CPU
).
Figure
OSC2
23): Slow, Wait (Slow
Power saving modes
).
CPU
).
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