ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 30

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Supply, reset and clock management
30/188
Figure 14. Reset block diagram
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
Internal LVD reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
●
The device RESET pin acts as an output that is pulled low when V
V
The LVD filters spikes on V
Internal Watchdog reset
The reset sequence generated by a internal Watchdog counter overflow is shown in
Figure
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
DD
Power-On reset
Voltage Drop reset
< V
15.
IT-
RESET
(falling edge) as shown in
V
DD
DD
w(RSTL)out
R
larger than t
ON
Figure
.
Filter
DD
g(VDD)
supply can generally be provided by an external
15.
OSC
to avoid parasitic resets.
frequency.
generator
Pulse
DD
< V
Watchdog reset
LVD reset
IT+
Internal
reset
(rising edge) or
ST72324B
DD
is over