ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 25

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST72324B
5.3.5
Note:
Stack Pointer register (SP)
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by an LD
instruction.
When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure
●
●
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 10. Stack manipulation example
SP
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15
0
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
On return from interrupt, the SP is incremented and the context is popped from the
stack.
@ 0100h
@ 01FFh
SP
10.
14
0
subroutine
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
Call
13
0
PCH
PCL
12
0
SP
11
0
Interrupt
event
PCH
PCL
PCH
PCL
CC
A
X
10
0
SP
9
0
Push Y
PCH
PCH
PCL
PCL
CC
X
8
1
Figure
Y
A
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SP
7
10).
6
Pop Y
PCH
PCH
PCL
PCL
CC
A
X
Central processing unit (CPU)
5
SP
4
IRET
PCH
PCL
3
Reset value: 01 FFh
SP
2
or RSP
RET
1
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