emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 49

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emc163sp16k

Manufacturer Part Number
emc163sp16k
Description
1mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
Figure 36: Asynchronous WRITE Followed by Burst READ
Note:
1. Nondefault BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency, latency code 2 (3 clocks),
2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the
WAIT active LOW, WAIT asserted during delay.
device is transitioning to fixed-latency burst READs. A refresh opportunity must be provided every
either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
A/DQ[15:0]
UB#/LB#
A[19:16]
ADV#
WAIT
WE#
CLK
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
Valid Address
t
Valid Address
t
AS
AS
t
t
t
AVS
AVS
CW
t
VP
t
t
AVH
AVH
t
BW
t
WP
t
WC
t
DW
Data
t
DH
Note 2
49
t
CBPH
Valid Address
Valid Address
t
t
t
t
t
SP
SP
CSP
t
SP
KHTL
SP
t
SP
t
HD
t
t
HD
t
HD
t
CLK
HD
t
CEM. A refresh opportunity is satisfied by
V
V
OH
OL
1Mx16 CellularRAM AD-MUX
t
BOE
t
ACLK
Output
Valid
Don’t Care
EMC163SP16K
Output
t
Valid
KOH
Output
Valid
Output
Valid
Undefined
t
HD
High-Z
t
OHZ

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