emc163sp16k Emlsi Inc., emc163sp16k Datasheet - Page 18

no-image

emc163sp16k

Manufacturer Part Number
emc163sp16k
Description
1mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
Note:
1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh
code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
collisions require a corresponding number of additional CE# LOW cycles.
(except A[19:18])
A/DQ[15:0]
A[19:18]
LB#/UB#
A[19:16]
ADV#
WAIT
WE#
CLK
CRE
OE#
CE#
2
High-Z
Latch control register value
t
CSP
t
OPCODE
t
t
t
OPCODE
SP
SP
SP
SP
t
KHTL
t
t
t
t
HD
HD
HD
HD
Note3
Latch control register address
18
t
CBPH
High-Z
Address
Address
Address
1Mx16 CellularRAM AD-MUX
EMC163SP16K
Don’t Care
Valid
data

Related parts for emc163sp16k