EMD12324P Emlsi Inc., EMD12324P Datasheet
EMD12324P
Related parts for EMD12324P
EMD12324P Summary of contents
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... The attached datasheets provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. History Initial Draft Homepage : www.emlsi.com 1 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 ...
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... Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. GENERAL DESCRIPTION This EMD12324P is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is organized as 8,192 rows by 512columns by 32 bits, fabricated with EMLSI’s high performance CMOS technology ...
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... Used to capture write data. For x32 device, DQS0 corresponds DQS0~DQS3 I/O to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31 VDD Supply Power Supply EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Descriptions 3 Preliminary Rev 0.0 ...
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... Precharge PREALL EMRS = Ext. Mode Reg. Set MRS = Mode Register Set PRE = Precharge PREALL = Precharge All Banks REFA = Auto Refresh REFS = Enter Self Refresh 4 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Self Refresh Auto REFA Refresh Precharge Power Down Burst ...
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... BANK MEMORY ARRAY 8,192 (8,192 x 256 x 64 SENSE AMPLIFIERS 64 256 COLUMN - 64 I/O GATING ADDRESS DM MASK LOGIC DECODER Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM DQS 4 4 GENERATOR DQS DRIVER Dout Dout Parallel DRIVER to Serial Din 32 32 ...
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... 1.8V 1.8V DDQ A ¥ ¥ ¥ ¥ Symbol C IN1 C IN2 C out C IN3 6 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Value -0.5 ~ 2.5 -0.5 ~ 2.5 -55 ~ +150 1 for Extended) Max Unit 1. 0.3 V DDQ 0 0 DDQ 2 © 5 © ...
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... SWITCHING; data CKmin = t CK CKmin = t ; continuous write bursts; CK CKmin = t ; burst refresh; CKE is HIGH; RC RFCmin TCSR Range 1/2 of Full Array 1/4 of Full Array 7 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM £ £ Version -60 -75 100 CKmin 0.6 0 ...
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... DDQ 0.5 V DDQ 1.0 0.5 V DDQ 0.4 V (Min) / 0.6 DDQ See Figure 2 (DC -0.1 DDQ OH ¨ (DC 0.1 DDQ OL Output ¨ Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Unit Note V V DDQ (Max DDQ Vtt=0 Z0= Figure 2. AC Output Load Circuit V DDQ Rev 0.0 ...
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... HZ t 0.6 DQSQ QHS t 0.65 QHS t 1.25 0.75 DQSS t 0.6 0.4 DQSH t 0.6 0.4 DQSL t 0.2 DSS t 0.2 DSH t 2 MRD t 0 WPRES t 0.6 0.4 WPST t 0.25 WPRE 9 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM -75 Unit Note Min Max 2.5 6 2.5 6 0.45 0. 0.45 0.55 CK min 7.5 100 ns 12 100 ns 1.0 ns 4,5 1.0 ns 4,5 2 ...
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... XSR CKE t 64 REF ∆t IS (ps) 0 +50 +100 /t in the case where the input slew rate is below 1.0V/ns Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM -75 Unit Note Min Max 1.1 t 0.5 CK 1.1 t 0.9 CK 0 100,000 ...
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... I/O slew rate is below 1.0V/ns. DH ∆t DS (ps) 0 +50 +100 /t in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM ∆t DH (ps) 0 +75 +150 ∆t DH (ps) 0 +50 +100 Rev 0 ...
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... Note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. Issue NOP or DESELECT commands for at least tMRD time. 11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command. 512M: 16M x 32 Mobile DDR SDRAM 12 Preliminary EMD12324P Rev 0.0 ...
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... A0-A6 set to the desired values. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. 512M: 16M x 32 Mobile DDR SDRAM 13 Preliminary EMD12324P Rev 0.0 ...
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... This will eliminate timing violations that may otherwise occur during normal operational accesses. 512M: 16M x 32 Mobile DDR SDRAM BA1=0 BA1=0 BA1=0 BA0=0 BA0=0 BA0=1 BA0=1 BA1=1 BA1=1 BA1=1 BA0=0 BA0=1 BA0=0 BA0=1 - 1/4 Array - 1/2 Array 14 Preliminary EMD12324P Partial Self Refresh Area BA1=0 BA1=1 Rev 0.0 ...
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... Reserved Reserved Reserved Mode Register Set Clock min Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM CAS Latency BT Burst Length Burst Type Burst Length Type Sequential 0 0 Interleave 0 0 Mode Select ...
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... Self Refresh Current ( 1/2 of Full Array 1/4 of Full Array 500 250 , Max Preliminary EMD12324P PASR RFU PASR A0 Size of Refreshed Array 0 0 Full Array 0 1 1/2 of Full Array 1 0 1/4 of Full Array 1 1 Reserved 0 0 Reserved ...
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... Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Interleave 0 1 Interleave Interleave ...
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... READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state the pre- viously open row is already in the process of precharging. 512M: 16M x 32 Mobile DDR SDRAM 18 Preliminary EMD12324P Rev 0.0 ...
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... The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later. Auto Refresh CKB CK Command PRE CKE = High t RP 512M: 16M x 32 Mobile DDR SDRAM Auto Refresh t RFC 19 Preliminary EMD12324P CMD Rev 0.0 ...
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... This mode is entered by having all banks idle then rising edge of the clock, while CKE is LOW. This mode is exited by asserting CKE HIGH. 512M: 16M x 32 Mobile DDR SDRAM t XSR t IS and WEB held LOW with RASB and CASB held HIGH at the CSB 20 Preliminary EMD12324P Active CMD Rev 0.0 ...
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... Activate Bank A Col. Addr. ) RCD Write NOP with Auto Precharge Row Cycle Time(tRC) 21 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM and RASB low at the rising edge of CSB Tn Tn+1 Tn+2 Bank B Bank A Row Addr. Row. Addr. RAS - RAS delay time(t ) RRD Bank B ...
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... CKB CK Command READ NOP t RPRE DQS CL2 DQ’s DQS CL3 DQ’ NOP NOP NOP t RPST Dout 0 Dout 1 Dout 2 Dout 3 t RPRE Dout 0 Dout 1 Dout 2 Dout 3 22 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM NOP NOP NOP NOP 8 Rev 0.0 ...
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... WRITE NOP Dout 0 Dout 1 Din 1 Din NOP NOP NOP Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Interrupted by precharge 23 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM NOP NOP NOP NOP NOP NOP NOP NOP Din 2 Din 3 5 ...
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... Burst Write Operation < Burst Length=4 > CKB CK Command WRITE A NOP t DQSSmax DQS t t DSH WPRES DQ’ NOP WRITE B NOP t DSS Din a0 Din a1 Din a2 Din a3 Din b0 Din b1 Din b2 Din b3 24 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM NOP NOP NOP NOP 8 Rev 0.0 ...
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... Din 0 Din 1 Din 2 Din 3 Din 4 t WTR t DSS t WPRE Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 25 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM NOP NOP NOP NOP READ NOP Din 7 Dout 0 Dout 1 Dout 2 Dout 3 Din 5 Din 6 Din 6 Din 7 ...
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... NOP NOP The burst ends after a delay equal to the CAS latency. Dout0 Dout1 Dout0 Dout1 NOP NOP NOP Din 4 Din 5 Din 6 Din 7 26 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM NOP Precharge A WRITE B t DQSSmax DQSSmin Din b0 Din b1 ...
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... Auto Precharge t RAS(min.) Begin Auto-Precharge WRITE NOP NOP NOP Auto Precharge Din 0 Din 1 Din 2 Din 3 27 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM NOP NOP NOP Dout0 Dout1 Dout2 Dout3 Dout0 Dout1 Dout2 Dout3 7 ...
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... NOP or DESELECT command). NOPs or DESELECT commands must be maintained on the command bus until t is satisfied. Power down CKB CK Precharge power Command Precharge Entry CKE = High down 28 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Active Active power power Active down down Entry Exit ...
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... after the end of burst Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM A11,A12 WEB BA0,1 A10/ CODE Row Address L Column Address ...
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... HIGH BAa DISABLE AUTO PRECHARGE Ca t RPRE Qa0 Qa1 Qa2 Qa3 READ t RPST DQS Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM BAb DISABLE AUTO PRECHARGE DQSS DSC Hi-Z RPST WPRE ...
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... DQ DM COMMAND ACTIVE HIGH BAb BAa BAb Rb DISABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE Rb Ca Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 ACTIVE READ READ 31 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 10 ...
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... COMMAND ACTIVE HIGH BAb BAa BAb Rb DISABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE Rb Ca Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 t RCD ACTIVE WRITE WRITE 32 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 10 ...
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... At burst read/write with auto precharge, CAS interrupt of the same is illegal HIGH Auto Precharge start(Note 1) Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 33 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM BAa ACTIVE Rev 0.0 10 ...
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... The new read/write command of another activated bank can be issued from this point At burst read/write with auto precharge, CAS interrupt of the same bank/another bank is illegal HIGH 34 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM BAa Auto Precharge start(Note DAL ACTIVE Rev 0 ...
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... CSB RASB CASB BA0,BA1 BAa A10/AP DISABLE AUTO PRECHARGE ADDR Ca WEB DQS DQ Da0 Da1 Da2 Da3 DM COMMAND WRITE HIGH BAa SINGLE BANK t WR PRE CHARGE 35 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 10 ...
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... COMMAND WRITE HIGH BAa BAb SINGLE BANK DISABLE AUTO PRECHARGE PRE WRITE CHARGE 36 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM BAc Cb Cc Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dc4 Dc5 t CCD WRITE Rev 0.0 10 ...
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... DQS DQ DM COMMAND WRITE HIGH BAb DISABLE AUTO PRECHARGE Cb Da0 Da1 Da2 Da3 Da4 Da5 t WTR READ 37 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 Rev 0.0 10 ...
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... A new Bank Activate command may be issued to the same bank after tRP HIGH BAa ALL BANK 2 t valid CK Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 PRE CHARGE 38 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 10 ...
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... DISABLE AUTO PRECHARGE ADDR Ca WEB DQS DQ DM COMMAND READ HIGH BAb DISABLE AUTO PRECHARGE Cb Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7 Qa0 Qa1 Burst WRITE stop 39 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 10 ...
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... BAa A10/AP DISABLE AUTO PRECHARGE ADDR Ca WEB DQS COMMAND READ HIGH BAb Cb Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 CCD READ 40 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Qb6 Qb7 Rev 0.0 10 ...
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... CKE CSB RASB CASB BA0,BA1 BAa A10/AP DISABLE AUTO PRECHARGE ADDR Ca WEB DQS DQ DM COMMAND WRITE HIGH Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 41 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 10 ...
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... NOPs or DESELECTs are required during this time NOP PRE T=200us RFC and CK stable 42 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM 3 MRS EMRS ACT NOP CODE CODE CODE CODE BA0=L ...
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... Precharge Command All Bank Note 1 Power & Clock must be stable for 200us before precharge all banks HIGH 2 Clock min. RP Any Command Mode Register Set Command 43 Preliminary EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 10 ...
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... Bank 2 ----------------------- 2 Bank 4 ----------------------- 4 Bank 6. Interface ( VDD,VDDQ ) V ------------------------- LVTTL ( 3.3V,3.3V ) H------------------------- LVTTL ( 3.3V,2. ------------------------- LVTTL ( 3.0V,3. ------------------------- LVTTL ( 3.0V,2. ------------------------- P-LVTTL ( 3.0V,1. ------------------------- LVCMOS ( 2.5V,2. ------------------------- LVCMOS ( 2.5V,1. ------------------------- LVCMOS ( 1.8V,1.8V ) EMD12324P 512M: 16M x 32 Mobile DDR SDRAM 11. Temperature 7. Version Blank ----------------- 1st generation A ------------------------2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation 8. Package Blank ----------------- KGD U ------------------------44 TSOP2 P ----------------------- 48 FpBGA ...